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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:39:59 12/21/2014 
-- Design Name: 
-- Module Name:    UD2_5 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UD2_5 is
  port (
    PhaseNegative: in  std_logic;
    PhasePositive: in  std_logic;
    InterPositive: in  std_logic;
    InterNegative: in  std_logic;
    OCDNegative: in  std_logic;
    LPFin: in  std_logic;
    OutA: out std_logic;
    OutB: out std_logic;
    OCDLedPositive: out std_logic;
    LPFout: out std_logic
    );

end UD2_5;

architecture Behavioral of UD2_5 is

component DFFwithClear
  port ( 
      DocdQ : out std_logic;      -- Data output
		DocdQinv :out std_logic; 
      DocdCLK :in std_logic;      -- Clock input
      DocdCLRinv :in std_logic  -- Asynchronous clear input
  );
end component;

component DffwithPandC
   port(
      DintQ : out std_logic;      -- Data output
      DintCLK :in std_logic;      -- Clock input
      DintCLRinv :in std_logic;  -- Asynchronous clear input
      DintPREinv : in std_logic   -- Asynchronous set input
   );
end component;

for DFFoc: DFFwithClear use entity work.DFFwithClear(DFFCbody);
for DFFin: DFFwithPandC use entity work.DFFwithPandC(DFFPCbody);

signal WireA, WireB, WireC, WireD, WireE, WireF, WireG, WireH, WireI, WireJ, Wirek, WireL, WireM, WireN, WireP, WireQ, WireR, WireS : std_logic;

begin
	
	DFFoc: DFFwithClear port map(WireF, WireM, WireH, WireK);
	DFFin: DFFwithPandC port map(WireA, WireC, WireB, WireD);
	
	OutA <= WireR;  ----out start
	OutB <= WireS;
	LPFout <= WireD;
	OCDLedPositive <= WireM;  ----out end
	
	WireP <= PhaseNegative;  ----in start
	WireI <= PhasePositive;
	WIreL <= InterPositive;
	WireQ <= InterNegative;
	WireK <= OCDNegative;
	WireN <= LPFin;   ----in end
	
	--WireA 
	WireB <= not WireN;
	WIreC <= not WireI;
	WireD <= not WireE;
	WireE <= WireF and WireH;
	--WireF
	WireG <= not WireC;
	WireH <= WireL and WireJ;
	WireI <= not wireP;
	WireJ <= not WireQ;
	--WireK
	--WireL
	--WireM
	--WireN
	--WireO
	--WireP
	--WireQ
	WireR <= WireA and WireC;
	WireS <= WireA and WireG;
	
	
	
	
end Behavioral;
----------------------------------------------------------------------------------


--library declaration for the module.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Asynchronous Clear,Set and Clock Enable(negedge clock).
--Note that the clear input has the highest priority,preset being the next highest
--priority and clock enable having the lowest priority
entity DFFwithClear is
   port(
      DocdQ : out std_logic;      -- Data output
		DocdQinv :out std_logic; 
      DocdCLK :in std_logic;      -- Clock input
      DocdCLRinv :in std_logic  -- Asynchronous clear input
   );
end DFFwithClear;

architecture DFFCbody of DFFwithClear is  --architecture of the circuit.

begin  --"begin" statement for architecture.

process(DocdCLRinv,DocdCLK) --process with sensitivity list.
begin  --"begin" statment for the process.

    if (DocdCLRinv = '0') then  --Asynchronous clear input
           DocdQ <= '0';
			  DocdQinv <= '1';
    else
               if (rising_edge(DocdCLK) ) then
                  DocdQ <= '1';  
						DocdQinv <= '0';
              end if;
   end if;

end process;  --end of process statement.

end DFFCbody;
----------------------------------------------------------------------------------
--library declaration for the module.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Asynchronous Clear,Set and Clock Enable(negedge clock).
--Note that the clear input has the highest priority,preset being the next highest
--priority and clock enable having the lowest priority
entity DFFwithPandC is
   port(
      DintQ : out std_logic;      -- Data output
      DintCLK :in std_logic;      -- Clock input
      DintCLRinv :in std_logic;  -- Asynchronous clear input
      DintPREinv : in std_logic   -- Asynchronous set input
   );
end DFFwithPandC;

architecture DFFPCbody of DFFwithPandC is  --architecture of the circuit.

begin  --"begin" statement for architecture.

process(DintCLRinv,DintPREinv,DintCLK) --process with sensitivity list.
begin  --"begin" statment for the process.

    if (DintCLRinv = '0') then  --Asynchronous clear input
           DintQ <= '0';
    else
           if(DintPREinv = '0') then  --Asynchronous set input
               DintQ <= '1';
           else
               if ( rising_edge(DintCLK) ) then
                  DintQ <= '0';      
              end if;
          end if;
   end if;

end process;  --end of process statement.

end DFFPCbody;
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